// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) /* * Copyright (C) 2025, STMicroelectronics - All Rights Reserved * Author: STM32CubeMX code generation for STMicroelectronics. */ /dts-v1/; #include #include "stm32mp157.dtsi" #include "stm32mp15xc.dtsi" #include "stm32mp15xxac-pinctrl.dtsi" #define DECPROT(id, permissions, lock) id permissions lock / { model = "STM32MP157C DCM"; compatible = "st,stm32mp157c-custom", "st,stm32mp157"; memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x40000000>; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; optee_memory: optee@de000000 { reg = <0xde000000 0x02000000>; no-map; }; }; aliases { mmc0 = &sdmmc1; mmc1 = &sdmmc2; usb0 = &usbotg_hs; spi0 = &qspi; serial0 = &usart1; serial1 = &usart2; serial2 = &usart3; }; chosen { #address-cells = <1>; #size-cells = <1>; ranges; stdout-path = "serial1:115200n8"; }; clocks { #ifndef CONFIG_TFABOOT clk_lsi: clk-lsi { clock-frequency = <32000>; }; clk_hsi: clk-hsi { clock-frequency = <64000000>; }; clk_csi: clk-csi { clock-frequency = <4000000>; }; clk_lse: clk-lse { clock-frequency = <32768>; st,css; }; clk_hse: clk-hse { clock-frequency = <24000000>; }; #endif /*CONFIG_TFABOOT*/ }; /* OP-TEE Node */ optee { compatible = "linaro,optee-tz"; method = "smc"; status = "okay"; firmware-name = "tee-header_v2.bin", "tee-pageable_v2.bin", "tee-pager_v2.bin"; }; /* Boot-Geräte-Konfiguration */ boot_devices { compatible = "st,stm32mp1-boot-device"; st,boot-device = "sdmmc1", "sdmmc2"; st,boot-part = <2>; /* Boot-Partition */ }; }; &pinctrl { /* SDMMC1 sd-card */ sdmmc1_pins_mx: sdmmc1_mx-0 { pins1 { pinmux = , /* SDMMC1_D0 */ , /* SDMMC1_D1 */ , /* SDMMC1_D2 */ , /* SDMMC1_D3 */ ; /* SDMMC1_CMD */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* SDMMC1_CK */ bias-disable; drive-push-pull; slew-rate = <3>; }; }; sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 { pins1 { pinmux = , /* SDMMC1_D0 */ , /* SDMMC1_D1 */ , /* SDMMC1_D2 */ ; /* SDMMC1_D3 */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* SDMMC1_CK */ bias-disable; drive-push-pull; slew-rate = <3>; }; pins3 { pinmux = ; /* SDMMC1_CMD */ bias-disable; drive-open-drain; slew-rate = <1>; }; }; sdmmc1_cd_pins: sdmmc1_cd_pins-0 { pins { u-boot,dm-pre-reloc; pinmux = ; /* SD_DETECT */ bias-pull-up; }; }; /* SDMMC2 eMMC */ sdmmc2_pins_mx: sdmmc2_mx-0 { pins1 { pinmux = , /* SDMMC2_D0 */ , /* SDMMC2_D1 */ , /* SDMMC2_D2 */ , /* SDMMC2_D3 */ , /* SDMMC2_D4 */ , /* SDMMC2_D5 */ , /* SDMMC2_D6 */ , /* SDMMC2_D7 */ ; /* SDMMC2_CMD */ bias-pull-up; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* SDMMC2_CK */ bias-pull-up; drive-push-pull; slew-rate = <3>; }; }; sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 { pins1 { pinmux = , /* SDMMC2_D0 */ , /* SDMMC2_D1 */ , /* SDMMC2_D2 */ , /* SDMMC2_D3 */ , /* SDMMC2_D4 */ , /* SDMMC2_D5 */ , /* SDMMC2_D6 */ ; /* SDMMC2_D7 */ bias-pull-up; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* SDMMC2_CK */ bias-pull-up; drive-push-pull; slew-rate = <3>; }; pins3 { pinmux = ; /* SDMMC2_CMD */ bias-pull-up; drive-open-drain; slew-rate = <1>; }; }; usart2_pins_mx: usart2_mx-0 { pins1 { pinmux = ; /* USART2_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { pinmux = ; /* USART2_RX */ bias-disable; }; }; }; &pinctrl_z { i2c4_pins_z_mx: i2c4_mx-0 { u-boot,dm-pre-reloc; pins { u-boot,dm-pre-reloc; pinmux = , /* I2C4_SCL */ ; /* I2C4_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; }; /* UART für Konsolenausgabe */ &usart2 { pinctrl-names = "default"; pinctrl-0 = <&usart2_pins_mx>; status = "okay"; }; /* SD-Karte für Boot */ &sdmmc1 { pinctrl-names = "default", "opendrain"; pinctrl-0 = <&sdmmc1_pins_mx &sdmmc1_cd_pins>; pinctrl-1 = <&sdmmc1_opendrain_pins_mx>; clocks = <&rcc SDMMC1_K>; resets = <&rcc SDMMC1_R>; max-frequency = <120000000>; status = "okay"; cd-gpios = <&gpiof 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,neg-edge; bus-width = <4>; vmmc-supply = <&v3v3>; secure-status ="okay"; /* Für OP-TEE wichtig */ }; /* eMMC für Boot */ &sdmmc2 { pinctrl-names = "default", "opendrain"; pinctrl-0 = <&sdmmc2_pins_mx>; pinctrl-1 = <&sdmmc2_opendrain_pins_mx>; clocks = <&rcc SDMMC2_K>; resets = <&rcc SDMMC2_R>; max-frequency = <120000000>; status = "okay"; non-removable; no-sd; no-sdio; st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; vqmmc-supply = <&v3v3>; mmc-ddr-3_3v; secure-status ="okay"; /* Für OP-TEE wichtig */ }; /* I2C4 für PMIC-Zugriff */ &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_z_mx>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; status = "okay"; pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; status = "okay"; regulators { compatible = "st,stpmic1-regulators"; vddcore: buck1 { u-boot,dm-pre-reloc; regulator-name = "vddcore"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-over-current-protection; }; vdd_ddr: buck2 { u-boot,dm-pre-reloc; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-over-current-protection; }; vdd: buck3 { u-boot,dm-pre-reloc; regulator-name = "vdd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-over-current-protection; }; v3v3: buck4 { u-boot,dm-pre-reloc; regulator-name = "v3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-over-current-protection; }; vdd_usb: ldo4 { u-boot,dm-pre-reloc; regulator-name = "vdd_usb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; vdda: ldo5 { u-boot,dm-pre-reloc; regulator-name = "vdda"; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; regulator-boot-on; }; }; }; }; &gpioa { /* Kommunikation mit U-Boot über Pins */ boot_control0: boot_control0 { gpio-hog; gpios = <6 GPIO_ACTIVE_LOW>; /* PA6 */ input; line-name = "boot_control0"; }; boot_control1: boot_control1 { gpio-hog; gpios = <15 GPIO_ACTIVE_LOW>; /* PA15 */ input; line-name = "boot_control1"; }; }; &rcc { #address-cells = <1>; #size-cells = <0>; status = "okay"; /* USER CODE BEGIN rcc */ compatible = "st,stm32mp1-rcc-secure"; /* USER CODE END rcc */ st,clksrc = < 0x0 /* CLK_CKPER_HSE */ 0x4 /* CLK_ETH_PLL4P */ 0x4 /* CLK_SDMMC12_PLL4P */ 0x0 /* CLK_STGEN_HSE */ 0x0 /* CLK_USBPHY_HSE */ 0x3 /* CLK_SPI2S1_PLL3Q */ 0x3 /* CLK_SPI2S23_PLL3Q */ 0x1 /* CLK_I2C46_HSI */ 0x5 /* CLK_USBO_USBPHY */ 0x0 /* CLK_ADC_CKPER */ 0x3 /* CLK_CEC_LSE */ 0x1 /* CLK_I2C12_HSI */ 0x1 /* CLK_UART24_HSI */ 0x3 /* CLK_SAI2_PLL3Q */ 0x2 /* CLK_RNG1_CSI */ 0x0 /* CLK_MPU_PLL1P */ 0x0 /* CLK_AXI_PLL2P */ 0x0 /* CLK_MCU_PLL3P */ 0x3 /* CLK_RTC_LSE */ 0x0 /* CLK_MCO1_DISABLED */ 0x0 /* CLK_MCO2_DISABLED */ >; st,clkdiv = < 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 /* DIV(DIV_MPU,1) bis DIV(DIV_MCO2,0) */ >; st,pll_vco { pll2_vco_1066Mhz: pll2-vco-1066Mhz { src = <0>; /* HSE als Quelle (CLK_PLL12_HSE) */ divmn = <2 65>; frac = <0x1400>; }; pll3_vco_408Mhz: pll3-vco-408Mhz { src = <0>; /* HSE als Quelle (CLK_PLL3_HSE) */ divmn = <1 33>; }; pll4_vco_594Mhz: pll4-vco-594Mhz { src = <0>; /* HSE als Quelle (CLK_PLL4_HSE) */ divmn = <3 98>; }; }; pll2:st,pll@1 { compatible = "st,stm32mp1-pll"; reg = <1>; st,pll = <&pll2_cfg1>; pll2_cfg1: pll2_cfg1 { st,pll_vco = <&pll2_vco_1066Mhz>; st,pll_div_pqr = <1 0 0>; }; }; pll3:st,pll@2 { compatible = "st,stm32mp1-pll"; reg = <2>; st,pll = <&pll3_cfg1>; pll3_cfg1: pll3_cfg1 { st,pll_vco = <&pll3_vco_408Mhz>; st,pll_div_pqr = <1 16 36>; }; }; pll4:st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; st,pll = <&pll4_cfg1>; pll4_cfg1: pll4_cfg1 { st,pll_vco = <&pll4_vco_594Mhz>; st,pll_div_pqr = <5 7 7>; }; }; }; /* ETZPC (Extended TrustZone Protection Controller) Konfiguration */ &etzpc { st,decprot = < 21 1 0 /* SDMMC1: Non-secure Read/Write, Unlocked */ 22 1 0 /* SDMMC2: Non-secure Read/Write, Unlocked */ 30 1 0 /* USART2: Non-secure Read/Write, Unlocked */ 36 1 0 /* I2C4: Non-secure Read/Write, Unlocked */ 7 1 0 /* RNG1: Non-secure Read/Write, Unlocked */ 8 1 0 /* HASH1: Non-secure Read/Write, Unlocked */ 9 1 0 /* CRYP1: Non-secure Read/Write, Unlocked */ >; }; /* TAMP (Tamper) Konfiguration */ &tamp { status = "okay"; st,tamp_passive_nb-pins = <0>; st,tamp_passive_pins = <0>; st,tamp_active_nb-pins = <0>; st,tamp_active_pins = <0>; }; /* RNG Konfiguration */ &rng1 { status = "okay"; }; /* RTC Konfiguration */ &rtc { status = "okay"; }; /* Hash für Secure Boot-Funktionen */ &hash1 { status = "okay"; }; /* Crypto für Secure Boot-Funktionen */ &cryp1 { status = "okay"; }; /* Für TF-A spezifische Konfiguration */ &cpu0 { cpu-supply = <&vddcore>; }; &cpu1 { cpu-supply = <&vddcore>; }; /* &osc_calibration { csi-calibration{ status = "okay"; }; hsi-calibration{ status = "okay"; }; }; */ &pwr_regulators { system_suspend_supported_soc_modes = < 0x1 /* STM32_PM_CSLEEP_RUN */ 0x4 /* STM32_PM_CSTOP_ALLOW_LP_STOP */ 0x5 /* STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR */ >; system_off_soc_mode = <0x7>; /* STM32_PM_SHUTDOWN */ vdd-supply = <&vddcore>; };