518 lines
13 KiB
Plaintext
518 lines
13 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
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* Author: STM32CubeMX code generation for STMicroelectronics.
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*/
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/dts-v1/;
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include "stm32mp157.dtsi"
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#include "stm32mp15xc.dtsi"
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#include "stm32mp15xxac-pinctrl.dtsi"
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#define DECPROT(id, permissions, lock) id permissions lock
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/ {
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model = "STM32MP157C DCM";
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compatible = "st,stm32mp157c-custom", "st,stm32mp157";
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memory@c0000000 {
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device_type = "memory";
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reg = <0xc0000000 0x40000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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optee_memory: optee@de000000 {
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reg = <0xde000000 0x02000000>;
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no-map;
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};
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};
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aliases {
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mmc0 = &sdmmc1;
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mmc1 = &sdmmc2;
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usb0 = &usbotg_hs;
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spi0 = &qspi;
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serial0 = &usart1;
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serial1 = &usart2;
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serial2 = &usart3;
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};
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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stdout-path = "serial1:115200n8";
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};
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clocks {
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#ifndef CONFIG_TFABOOT
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clk_lsi: clk-lsi {
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clock-frequency = <32000>;
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};
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clk_hsi: clk-hsi {
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clock-frequency = <64000000>;
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};
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clk_csi: clk-csi {
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clock-frequency = <4000000>;
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};
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clk_lse: clk-lse {
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clock-frequency = <32768>;
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st,css;
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};
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clk_hse: clk-hse {
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clock-frequency = <24000000>;
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};
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#endif /*CONFIG_TFABOOT*/
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};
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/* OP-TEE Node */
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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status = "okay";
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firmware-name = "tee-header_v2.bin", "tee-pageable_v2.bin", "tee-pager_v2.bin";
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};
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/* Boot-Geräte-Konfiguration */
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boot_devices {
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compatible = "st,stm32mp1-boot-device";
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st,boot-device = "sdmmc1", "sdmmc2";
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st,boot-part = <2>; /* Boot-Partition */
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};
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};
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&pinctrl {
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/* SDMMC1 sd-card */
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sdmmc1_pins_mx: sdmmc1_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('E', 6, AF8 )>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
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<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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bias-disable;
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drive-push-pull;
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slew-rate = <1>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('E', 6, AF8 )>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
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bias-disable;
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drive-push-pull;
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slew-rate = <1>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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};
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pins3 {
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pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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bias-disable;
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drive-open-drain;
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slew-rate = <1>;
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};
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};
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sdmmc1_cd_pins: sdmmc1_cd_pins-0 {
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pins {
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u-boot,dm-pre-reloc;
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pinmux = <STM32_PINMUX('F', 2, GPIO)>; /* SD_DETECT */
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bias-pull-up;
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};
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};
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/* SDMMC2 eMMC */
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sdmmc2_pins_mx: sdmmc2_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9 )>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF9 )>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF9 )>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF9 )>, /* SDMMC2_D3 */
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<STM32_PINMUX('A', 8, AF9 )>, /* SDMMC2_D4 */
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<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
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<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
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<STM32_PINMUX('D', 3, AF9 )>, /* SDMMC2_D7 */
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<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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bias-pull-up;
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drive-push-pull;
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slew-rate = <1>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('E', 3, AF9 )>; /* SDMMC2_CK */
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bias-pull-up;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9 )>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF9 )>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF9 )>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF9 )>, /* SDMMC2_D3 */
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<STM32_PINMUX('A', 8, AF9 )>, /* SDMMC2_D4 */
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<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
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<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
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<STM32_PINMUX('D', 3, AF9 )>; /* SDMMC2_D7 */
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bias-pull-up;
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drive-push-pull;
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slew-rate = <1>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('E', 3, AF9 )>; /* SDMMC2_CK */
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bias-pull-up;
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drive-push-pull;
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slew-rate = <3>;
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};
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pins3 {
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pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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bias-pull-up;
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drive-open-drain;
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slew-rate = <1>;
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};
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};
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usart2_pins_mx: usart2_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('F', 5, AF7)>; /* USART2_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('F', 4, AF7)>; /* USART2_RX */
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bias-disable;
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};
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};
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};
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&pinctrl_z {
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i2c4_pins_z_mx: i2c4_mx-0 {
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u-boot,dm-pre-reloc;
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pins {
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u-boot,dm-pre-reloc;
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pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
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<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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};
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/* UART für Konsolenausgabe */
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&usart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&usart2_pins_mx>;
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status = "okay";
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};
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/* SD-Karte für Boot */
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&sdmmc1 {
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pinctrl-names = "default", "opendrain";
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pinctrl-0 = <&sdmmc1_pins_mx &sdmmc1_cd_pins>;
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pinctrl-1 = <&sdmmc1_opendrain_pins_mx>;
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clocks = <&rcc SDMMC1_K>;
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resets = <&rcc SDMMC1_R>;
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max-frequency = <120000000>;
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status = "okay";
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cd-gpios = <&gpiof 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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disable-wp;
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st,neg-edge;
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bus-width = <4>;
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vmmc-supply = <&v3v3>;
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secure-status ="okay"; /* Für OP-TEE wichtig */
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};
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/* eMMC für Boot */
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&sdmmc2 {
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pinctrl-names = "default", "opendrain";
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pinctrl-0 = <&sdmmc2_pins_mx>;
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pinctrl-1 = <&sdmmc2_opendrain_pins_mx>;
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clocks = <&rcc SDMMC2_K>;
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resets = <&rcc SDMMC2_R>;
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max-frequency = <120000000>;
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status = "okay";
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non-removable;
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no-sd;
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no-sdio;
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st,neg-edge;
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bus-width = <8>;
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vmmc-supply = <&v3v3>;
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vqmmc-supply = <&v3v3>;
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mmc-ddr-3_3v;
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secure-status ="okay"; /* Für OP-TEE wichtig */
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};
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/* I2C4 für PMIC-Zugriff */
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_z_mx>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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clock-frequency = <400000>;
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status = "okay";
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pmic: stpmic@33 {
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compatible = "st,stpmic1";
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reg = <0x33>;
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status = "okay";
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regulators {
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compatible = "st,stpmic1-regulators";
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vddcore: buck1 {
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u-boot,dm-pre-reloc;
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regulator-name = "vddcore";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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vdd_ddr: buck2 {
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u-boot,dm-pre-reloc;
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regulator-name = "vdd_ddr";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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vdd: buck3 {
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u-boot,dm-pre-reloc;
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regulator-name = "vdd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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v3v3: buck4 {
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u-boot,dm-pre-reloc;
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regulator-name = "v3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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vdd_usb: ldo4 {
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u-boot,dm-pre-reloc;
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regulator-name = "vdd_usb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdda: ldo5 {
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u-boot,dm-pre-reloc;
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regulator-name = "vdda";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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regulator-boot-on;
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};
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};
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};
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};
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&gpioa {
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/* Kommunikation mit U-Boot über Pins */
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boot_control0: boot_control0 {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_LOW>; /* PA6 */
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input;
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line-name = "boot_control0";
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};
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boot_control1: boot_control1 {
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gpio-hog;
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gpios = <15 GPIO_ACTIVE_LOW>; /* PA15 */
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input;
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line-name = "boot_control1";
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};
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};
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&rcc {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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/* USER CODE BEGIN rcc */
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compatible = "st,stm32mp1-rcc-secure";
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/* USER CODE END rcc */
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st,clksrc = <
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0x0 /* CLK_CKPER_HSE */
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0x4 /* CLK_ETH_PLL4P */
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0x4 /* CLK_SDMMC12_PLL4P */
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0x0 /* CLK_STGEN_HSE */
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0x0 /* CLK_USBPHY_HSE */
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0x3 /* CLK_SPI2S1_PLL3Q */
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0x3 /* CLK_SPI2S23_PLL3Q */
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0x1 /* CLK_I2C46_HSI */
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0x5 /* CLK_USBO_USBPHY */
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0x0 /* CLK_ADC_CKPER */
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0x3 /* CLK_CEC_LSE */
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0x1 /* CLK_I2C12_HSI */
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0x1 /* CLK_UART24_HSI */
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0x3 /* CLK_SAI2_PLL3Q */
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0x2 /* CLK_RNG1_CSI */
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0x0 /* CLK_MPU_PLL1P */
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0x0 /* CLK_AXI_PLL2P */
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0x0 /* CLK_MCU_PLL3P */
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0x3 /* CLK_RTC_LSE */
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0x0 /* CLK_MCO1_DISABLED */
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0x0 /* CLK_MCO2_DISABLED */
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>;
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st,clkdiv = <
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1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 /* DIV(DIV_MPU,1) bis DIV(DIV_MCO2,0) */
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>;
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st,pll_vco {
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pll2_vco_1066Mhz: pll2-vco-1066Mhz {
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src = <0>; /* HSE als Quelle (CLK_PLL12_HSE) */
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divmn = <2 65>;
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frac = <0x1400>;
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};
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pll3_vco_408Mhz: pll3-vco-408Mhz {
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src = <0>; /* HSE als Quelle (CLK_PLL3_HSE) */
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divmn = <1 33>;
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};
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pll4_vco_594Mhz: pll4-vco-594Mhz {
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src = <0>; /* HSE als Quelle (CLK_PLL4_HSE) */
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divmn = <3 98>;
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};
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};
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pll2:st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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st,pll = <&pll2_cfg1>;
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pll2_cfg1: pll2_cfg1 {
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st,pll_vco = <&pll2_vco_1066Mhz>;
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st,pll_div_pqr = <1 0 0>;
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};
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};
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pll3:st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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st,pll = <&pll3_cfg1>;
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pll3_cfg1: pll3_cfg1 {
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st,pll_vco = <&pll3_vco_408Mhz>;
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st,pll_div_pqr = <1 16 36>;
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};
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};
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pll4:st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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st,pll = <&pll4_cfg1>;
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pll4_cfg1: pll4_cfg1 {
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st,pll_vco = <&pll4_vco_594Mhz>;
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st,pll_div_pqr = <5 7 7>;
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};
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};
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};
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/* ETZPC (Extended TrustZone Protection Controller) Konfiguration */
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&etzpc {
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st,decprot = <
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21 1 0 /* SDMMC1: Non-secure Read/Write, Unlocked */
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22 1 0 /* SDMMC2: Non-secure Read/Write, Unlocked */
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30 1 0 /* USART2: Non-secure Read/Write, Unlocked */
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36 1 0 /* I2C4: Non-secure Read/Write, Unlocked */
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7 1 0 /* RNG1: Non-secure Read/Write, Unlocked */
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8 1 0 /* HASH1: Non-secure Read/Write, Unlocked */
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9 1 0 /* CRYP1: Non-secure Read/Write, Unlocked */
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>;
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};
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/* TAMP (Tamper) Konfiguration */
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&tamp {
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status = "okay";
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st,tamp_passive_nb-pins = <0>;
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st,tamp_passive_pins = <0>;
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st,tamp_active_nb-pins = <0>;
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st,tamp_active_pins = <0>;
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};
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/* RNG Konfiguration */
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&rng1 {
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status = "okay";
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};
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/* RTC Konfiguration */
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&rtc {
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status = "okay";
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};
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/* Hash für Secure Boot-Funktionen */
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&hash1 {
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status = "okay";
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};
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/* Crypto für Secure Boot-Funktionen */
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&cryp1 {
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status = "okay";
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};
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/* Für TF-A spezifische Konfiguration */
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&cpu0 {
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cpu-supply = <&vddcore>;
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};
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&cpu1 {
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|
cpu-supply = <&vddcore>;
|
|
};
|
|
/*
|
|
&osc_calibration {
|
|
|
|
csi-calibration{
|
|
status = "okay";
|
|
};
|
|
|
|
hsi-calibration{
|
|
status = "okay";
|
|
};
|
|
};
|
|
*/
|
|
&pwr_regulators {
|
|
system_suspend_supported_soc_modes = <
|
|
0x1 /* STM32_PM_CSLEEP_RUN */
|
|
0x4 /* STM32_PM_CSTOP_ALLOW_LP_STOP */
|
|
0x5 /* STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR */
|
|
>;
|
|
system_off_soc_mode = <0x7>; /* STM32_PM_SHUTDOWN */
|
|
vdd-supply = <&vddcore>;
|
|
};
|
|
|