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meta-dcm/conf/machine/include/stm32mp157c-dcm-u-boot.dts

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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32MP157F-DK2 STM32CubeMX board - u-boot";
compatible = "st,stm32mp157f-dk2-2-mx", "st,stm32mp157f-dk2", "st,stm32mp157";
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
aliases {
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
usb0 = &usbotg_hs;
spi0 = &qspi;
serial0 = &usart1;
serial1 = &usart2;
serial2 = &usart3;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial1:115200n8";
};
config {
u-boot,mmc-env-partition = "ssbl";
};
clocks {
#ifndef CONFIG_TFABOOT
clk_lsi: clk-lsi {
clock-frequency = <32000>;
};
clk_hsi: clk-hsi {
clock-frequency = <64000000>;
};
clk_csi: clk-csi {
clock-frequency = <4000000>;
};
clk_lse: clk-lse {
clock-frequency = <32768>;
st,css;
};
clk_hse: clk-hse {
clock-frequency = <24000000>;
};
#endif /*CONFIG_TFABOOT*/
};
};
&pinctrl {
u-boot,dm-pre-reloc;
sdmmc1_pins_mx: sdmmc1_mx-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('E', 6, AF8 )>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('E', 6, AF8 )>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins3 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
bias-disable;
drive-open-drain;
slew-rate = <1>;
};
};
sdmmc1_cd_pins: sdmmc1_cd_pins-0 {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('F', 2, GPIO)>; /* SD_DETECT */
bias-pull-up;
};
};
sdmmc2_pins_mx: sdmmc2_mx-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('B', 14, AF9 )>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9 )>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF9 )>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9 )>, /* SDMMC2_D3 */
<STM32_PINMUX('A', 8, AF9 )>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, AF9 )>, /* SDMMC2_D7 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('E', 3, AF9 )>; /* SDMMC2_CK */
bias-pull-up;
drive-push-pull;
slew-rate = <2>;
};
};
sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('B', 14, AF9 )>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9 )>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF9 )>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9 )>, /* SDMMC2_D3 */
<STM32_PINMUX('A', 8, AF9 )>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, AF9 )>; /* SDMMC2_D7 */
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('E', 3, AF9 )>; /* SDMMC2_CK */
bias-pull-up;
drive-push-pull;
slew-rate = <2>;
};
pins3 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
bias-pull-up;
drive-open-drain;
slew-rate = <1>;
};
};
quadspi_pins_mx: quadspi_mx-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QUADSPI_BK1_NCS */
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins3 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QUADSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */
<STM32_PINMUX('F', 6, AF9)>; /* QUADSPI_BK1_IO3 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
};
usart2_pins_mx: usart2_mx-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('F', 5, AF7)>; /* USART2_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('F', 4, AF7)>; /* USART2_RX */
bias-disable;
};
};
eth1_pins_mx: eth1_mx-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RX_CLK */
<STM32_PINMUX('A', 7, AF11)>, /* ETH1_RX_CTL */
<STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RXD1 */
<STM32_PINMUX('H', 6, AF11)>, /* ETH1_RXD2 */
<STM32_PINMUX('B', 1, AF11)>, /* ETH1_RXD3 */
<STM32_PINMUX('G', 12, AF11)>; /* ETH1_PHY_INTN */
bias-disable;
};
pins2 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('B', 11, AF11)>, /* ETH1_TX_CTL */
<STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
<STM32_PINMUX('G', 4, AF11)>, /* ETH1_GTX_CLK */
<STM32_PINMUX('G', 5, AF11)>, /* ETH1_CLK125 */
<STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /* ETH1_TXD2 */
<STM32_PINMUX('E', 2, AF11)>; /* ETH1_TXD3 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
};
&pinctrl_z {
u-boot,dm-pre-reloc;
i2c4_pins_z_mx: i2c4_mx-0 {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
};
&rcc {
u-boot,dm-pre-reloc;
status = "okay";
};
/* UART für Konsolenausgabe */
&usart2 {
u-boot,dm-pre-reloc;
pinctrl-names = "default";
pinctrl-0 = <&usart2_pins_mx>;
status = "okay";
};
/* SD-Karte für Boot */
&sdmmc1 {
u-boot,dm-pre-reloc;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdmmc1_pins_mx &sdmmc1_cd_pins>;
pinctrl-1 = <&sdmmc1_opendrain_pins_mx>;
status = "okay";
cd-gpios = <&gpiof 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
};
/* eMMC für Boot */
&sdmmc2 {
u-boot,dm-pre-reloc;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdmmc2_pins_mx>;
pinctrl-1 = <&sdmmc2_opendrain_pins_mx>;
status = "okay";
non-removable;
no-sd;
no-sdio;
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
};
/* QSPI-Flash für Boot */
&qspi {
u-boot,dm-pre-reloc;
pinctrl-names = "default";
pinctrl-0 = <&quadspi_pins_mx>;
status = "okay";
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: w25q128@0 {
u-boot,dm-pre-reloc;
compatible = "winbond,w25q128", "jedec,spi-nor", "spi-flash";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
m25p,fast-read;
};
};
/* I2C4 für PMIC-Zugriff */
&i2c4 {
u-boot,dm-pre-reloc;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_z_mx>;
status = "okay";
clock-frequency = <400000>;
pmic: stpmic@33 {
u-boot,dm-pre-reloc;
compatible = "st,stpmic1";
reg = <0x33>;
status = "okay";
regulators {
compatible = "st,stpmic1-regulators";
vddcore: buck1 {
u-boot,dm-pre-reloc;
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_ddr: buck2 {
u-boot,dm-pre-reloc;
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd: buck3 {
u-boot,dm-pre-reloc;
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
};
v3v3: buck4 {
u-boot,dm-pre-reloc;
regulator-name = "v3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_usb: ldo4 {
u-boot,dm-pre-reloc;
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdda: ldo5 {
u-boot,dm-pre-reloc;
regulator-name = "vdda";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-boot-on;
};
};
};
};
/* USB OTG für Boot von USB-Geräten */
&usbotg_hs {
u-boot,dm-pre-reloc;
pinctrl-names = "default";
status = "okay";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
};
&usbphyc {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbphyc_port0 {
u-boot,dm-pre-reloc;
status = "okay";
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
u-boot,dm-pre-reloc;
status = "okay";
phy-supply = <&vdd_usb>;
};
/* Ethernet für Boot über Netzwerk (wenn benötigt) */
&ethernet0 {
pinctrl-names = "default";
pinctrl-0 = <&eth1_pins_mx>;
status = "okay";
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
st,eth-clk-sel = "true";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c22";
};
};
};
/* Hash für Secure Boot-Funktionen */
&hash1 {
u-boot,dm-pre-reloc;
status = "okay";
};
/* Crypto für Secure Boot-Funktionen */
&cryp1 {
u-boot,dm-pre-reloc;
status = "okay";
};
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